CDCE62005 Datasheet, PDF (6/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Interface and Control Block
The CDCE62005 is a highly flexible and configurable architecture and as such contains a number of registers so
that the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAM
determine device configuration at all times. On power-up, the CDCE62005 copies the contents of the EEPROM
into the RAM and the device begins operation based on the default configuration stored in the EEPROM.
Systems that do not have a host system to communicate with the CDCE62005 use this method for device
configuration. The CDCE62005 provides the ability to lock the EEPROM; enabling the designer to implement a
fault tolerant design. After power-up, the host system may overwrite the contents of the RAM via the SPI (Serial
Peripheral Interface) port. This enables the configuration and reconfiguration of the CDCE62005 during system
operation. Finally, the device offers the ability to copy the contents of the RAM into EEPROM, if the EEPROM is
unlocked.
REF_SELECT
/Power_Down
/SYNC
SPI_LE
SPI_CLK
SPI_MISO
SPI_MOSI
Interface
&
Control
Static RAM (Device Registers)
Register 8
Register 7
Register 6
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
Device
Hardware
EEPROM (Default Configuration)
Register 7
Register 6
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
Figure 4. CDCE62005 Interface and Control Block
6
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCE62005