CDCE62005 Datasheet, PDF (7/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
Input Block
The Input Block includes a pair of Universal Input Buffers and an Auxiliary Input. The Input Block buffers the
incoming signals and facilitates signal routing to the Internal Clock Distribution bus and the Synthesizer Block via
the smart multiplexer (called the Smart MUX). The Internal Clock Distribution Bus connects to all output blocks
discussed in the next section. Therefore, a clock signal present on the Internal Clock Distribution bus can appear
on any or all of the device outputs. The CDCE62005 routes the PRI_IN and SEC_IN inputs directly to the Internal
Clock Distribution Bus. Additionally, it can divide these signals via the dividers present on the inputs and output
of the first stage of the Smart MUX.
LVPECL: 1500 MHz
LVDS: 800 MHz
LVCMOS: 250 MHz
PRI_IN
SEC_IN
1500 MHz
1500 MHz
REF_SEL
Smart MUX
Control
Crystal: 2 MHz - 40 MHz
XTAL/
Single Ended: 2 MHz - 75 MHz AUX_IN
/1:/2:HiZ
/1:/2:HiZ
Smart
MUX1
Reference Divider
/1 - /8
Figure 5. CDCE62005 Input Block
Smart
MUX2
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCE62005
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