CDCE62005 Datasheet, PDF (37/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
State
Power
Down
Sleep
Sync
Table 14. CDCE62005 Device State Definitions (continued)
Device Behavior
Entered Via
Used to shut down all hardware and
Resets the device after exiting the
Power Down State. Therefore, the
EEPROM contents will eventually be
copied into RAM after the Power
Down State is exited.
Power_Down pin is pulled LOW.
Identical to the Power Down State
except the EEPROM contents are
not copied into RAM.
Sleep bit in device register 8 bit 7 is
set LOW.
Sync synchronizes all output
dividers so that they begin counting
at the same time. Note: this
operation is performed automatically
each time a divider register is
accessed.
Sync Bit in device register 8 bit 8 is
set LOW or Sync pin is pulled LOW
Exited Via
Power_Down pin is pulled HIGH.
Sleep bit in device register 8 bit 7 is set
HIGH.
Sync Bit in device register 8 bit 8 is set
HIGH or Sync pin is pulled HIGH
SPI Port
ON
Status
PLL
Output
Divider
Disabled Disabled
Output
Buffer
Disabled
ON
Disabled Disabled Disabled
ON
Enabled Disabled Disabled
External Control Pins
REF_SEL
REF_SEL provides a way to switch between the primary and secondary reference inputs (PRI_IN and SEC_IN)
via an external signal. It works in conjunction with the smart multiplexer discussed in the Input Block section.
Power_Down
The Power_Down pin places the CDCE62005 into the power down state . Additionally, the CDCE62005 loads
the contents of the EEPROM into RAM after the Power_Down pin is de-asserted; therefore, it is used to initialize
the device after power is applied. SPI_LE signal has to be HIGH in order for EEPROM to load correctly during
the rising edge of Power_Down.
SYNC
The SYNC pin (Active LOW) has a complementary register location located in Device Register 8 bit 8. When
enabled, Sync synchronizes all output dividers so that they begin counting simultaneously. Further, SYNC
disables all outputs when in the active. State.
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