CDCE62005 Datasheet, PDF (30/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Device Registers: Register 3
SPI RAM BIT NAME
BIT BIT
0
A0
1
A1
2
A2
3
A3
4
0 REFDIV2
5
1 RESERVED
6
2 RESERVED
7
3 RESERVED
8
4 OUTMUX3SELX
9
5 OUTMUX3SELY
10 6 PH3ADJC0
11 7 PH3ADJC1
12 8 PH3ADJC2
13 9 PH3ADJC3
14 10 PH3ADJC4
15 11 PH3ADJC5
16 12 PH3ADJC6
17 13 OUT3DIVRSEL0
18 14 OUT3DIVRSEL1
19 15 OUT3DIVRSEL2
20 16 OUT3DIVRSEL3
21 17 OUT3DIVRSEL4
22 18 OUT3DIVRSEL5
23 19 OUT3DIVRSEL6
24 20 OUT3DIVSEL
25 21 HiSWINGLVPEC3
26 22 CMOSMODE3PX
27 23 CMOSMODE3PY
28 24 CMOSMODE3NX
29 25 CMOSMODE3NY
30 26 OUTBUFSEL3X
31 27 OUTBUFSEL3Y
Table 8. CDCE62005 Register 3 Bit Definitions
RELATED
BLOCK
Reference
Divider
Address 0
Address 1
Address 2
Address 3
Reference Divider Bit “2”
DESCRIPTION/FUNCTION
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Used in Test Mode
Used in Test Mode
OUTPUT MUX “3” Select. Selects the Signal driving Output Divider”3”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE
Coarse phase adjust select for output divider “3”
OUTPUT DIVIDER “3” Ratio Select
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
LVCMOS mode select for OUTPUT “3” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
LVCMOS mode select for OUTPUT “3” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
OUTPUT TYPE
RAM BITS
22 23 24 25 26 27
LVPECL
00 0 0 0
1
LVDS
01 0 1 1
1
LVCMOS
See Settings Above* 0
0
Output Disabled
01 0 1 1
0
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
1
1
0
0
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
30
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