CDCE62005 Datasheet, PDF (39/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
Universal Input Buffers (UIB)
Figure 24 shows the key elements of a universal input buffer. A UIB supports multiple formats along with different
termination and coupling schemes. The CDCE62005 implements the UIB by including on board switched
termination, a programmable bias voltage generator, and an output multiplexer. The CDCE62005 provides a high
degree of configurability on the UIB to facilitate most existing clock input formats.
PRI_IN
Vbb
1 mF
SEC_IN
PN
50 Ω
50 Ω
PINV
PP
50 Ω
50 Ω
Universal Input Control
Vbb
Register 6
12
Settings
5.1
5.0
5.6 Nominal
INBUFSELY INBUFSELX ACDCSEL Vbb
1
0
0
1.9V
1
0
1
1.2V
1
1
0
1.2V
1
1
1
1.2V
Register 5
10 9 8 7 6 1 0
SN
SP
SINV
Settings
SWITCH Status
5.0
5.1
5.8, 6.12 5.9,5.10
INBUFSELX INBUFSELY TERMSEL INVBB
P
N
INV
0
0
X
X
OFF
OFF
OFF
X
X
1
X
OFF
OFF
OFF
X
1
0
0
ON
ON
ON
X
1
0
1
ON
ON
OFF
Figure 24. CDCE62005 Universal Input Buffer
Table 15 lists several settings for many possible clock input scenarios. Note that the two universal input buffers
share the Vbb generator. Therefore, if both inputs use internal termination, they must use the same configuration
mode (LVDS, LVPECL, or LVCMOS). If the application requires different modes (e.g. LVDS and LVPECL) then
one of the two inputs must implement external termination.
Table 15. CDCE62005 Universal Input Buffer Configuration Matrix
PRI_IN CONFIGURATION MATRIX
Register.Bit →
Bit Name →
5.7
HYSTEN
1
1
1
1
1
1
1
0
1
5.1
INBUFSELY
0
1
1
1
1
1
1
X
X
SETTINGS
5.0
5.8
INBUFSELX PRI_TERMSEL
0
X
0
0
0
0
0
1
1
0
1
0
1
1
X
X
X
X
5.9
PRIINVBB
X
0
0
X
0
0
X
X
X
5.6
ACDCSEL
X
0
1
X
0
1
X
X
X
Hysteresis
ENABLED
ENABLED
ENABLED
ENABLED
ENABLED
ENABLED
ENABLED
OFF
ENABLED
CONFIGURATION
Mode
LVCMOS
LVPECL
LVPECL
LVPECL
LVDS
LVDS
LVDS
—
—
Coupling
DC
AC
DC
—
AC
DC
—
—
—
Termination
N/A
Internal
Internal
External
Internal
Internal
External
—
—
Vbb
—
1.9V
1.2V
—
1.2V
1.2V
—
—
—
SEC_IN CONFIGURATION MATRIX
SETTINGS
CONFIGURATION
Register.Bit →
5.7
5.1
5.0
6.12
5.10
5.6
Bit Name →
HYSTEN INBUFSELY INBUFSELX SEC_TERMSEL SECINVBB ACDCSEL Hysteresis Mode Coupling Termination Vbb
1
0
0
X
X
X
ENABLED LVCMOS
DC
N/A
—
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