CDCE62005 Datasheet, PDF (10/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
COMPUTING THE OUTPUT FREQUENCY
Figure 9 presents the block diagram of the CDCE62005 in synthesizer mode highlighting the clock path for a
single output. It also identifies the following regions containing dividers comprising the complete clock path
• R: Includes the cumulative divider values of all dividers included from the Input Ports to the output of the
Smart Multiplexer (see Input Block for more details)
• O: The output divider value (see Output Block for more details)
• I: The input divider value (see Synthesizer Block for more details)
• P: The Prescaler divider value (see Synthesizer Block of more details)
• F: The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block for
more details)
O
Output
Divider 0
U 0P
F_OUT
U 0N
F_IN
R
/1:/2:HiZ
Reference
Divider
Output
U 1P
/1:/2:HiZ
Divider 1
U 1N
EXT_LFP
EXT_LFN
I
Input
Divider
Feedback
Divider
F
PFD /
CP
P
Prescaler
Output
Divider 2
Output
Divider 3
Output
Divider 4
U 2P
U 2N
U 3P
U 3N
U 4P
U 4N
AUX
OUT
Figure 9. CDCE62005 Clock Path – Synthesizer Mode
With respect to Figure 9, any output frequency generated by the CDCE62005 relates to the input frequency
connected to the Synthesizer Block by Equation 1.
F
F_OUT
= F_IN
´
R´I´O
(1)
Equation 1 holds true when subject to the following constraints:
1.750 Ghz < O x P x F_OUT< 2.356 GHz
And the comparison frequency F_COMP,
40 kHz ≤ F_COMP < 40 MHz
Where:
F_COMP
=
F_IN
R´I
(2)
Note: This device cannot output the frequencies between 780 MHz to 880 MHz
10
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