CDCE62005 Datasheet, PDF (18/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
TIMING REQUIREMENTS
over recommended ranges of supply voltage, load and operating free air temperature (unless otherwise noted)
PARAMETER
PRI_IN/SEC_IN_IN REQUIREMENTS
Maximum Clock Frequency Applied to PRI_IN & SEC_IN in fan-out mode
Maximum Clock Frequency Applied to Smart Multiplexer input Divider
f_{max Maximum Clock Frequency Applied to Reference Divider}
For Single ended Inputs ( LVCMOS) on PRI_IN and SEC_IN
Single duty cycle of PRI_IN or SEC_IN at V_CC / 2
Differential duty cycle of PRI_IN or SEC_IN at V_CC / 2
AUXILARY_IN REQUIREMENTS
f_REF Single ended Inputs (LVCMOS) on AUX_IN
f_REF Crystal single ended Inputs (AT-Cut Crystal Input)
PD, SYNC, REF_SEL REQUIREMENTS
t_r/ t_f Rise and fall time of the PD, SYNC, REF_SEL signal from 20% to 80% of V_CC
MIN TYP MAX
40%
40%
1500
500
250
250
60%
60%
2
75
2
42
4
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
ns
18
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