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CDCE62005 Datasheet, PDF (69/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
30.72 MHz
10.00 MHz
/1:/2:HiZ
/1:/2:HiZ
Reference
Divider
Output
Divider 0
Output
Divider 1
122 .88 MHz
491 .52 MHz
Input
Divider
Feedback
Divider
PFD/
CP
Prescaler
Output
Divider 2
Output
Divider 3
245 .76 MHz
30.72 MHz
30.72 MHz
Output
Divider 4
10 MHz
10 MHz
Figure 43. CDCE62005 Jitter Cleaner Example
Clocking ADCs with the CDCE62005
High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sample
clock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularly
implement receiver chains that take advantage of the characteristics of bandpass sampling. This implementation
trend often causes engineers working in communications system design to encounter the term clock limited
performance. Therefore, it is important to understand the impact of clock jitter on ADC performance. Equation 8
shows the relationship of data converter signal to noise ratio (SNR) to total jitter.
SNR jitter
=
20 log10
é
ê
1
ù
ú
ë 2πfin jittertotal û
(8)
Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sample
clock:
jittertotal = (jitterADC )2 + (jitterCLK )2
(9)
With respect to an ADC with N-bits of resolution, ignoring total jitter, DNL, and input noise, the following equation
shows the relationship between resolution and SNR:
SNRADC = 6.02N +1.76
(10)
Figure 44 plots Equation 8 and Equation 10 for constant values of total jitter. When used in conjunction with most
ADCs, the CDCE62005 supports a total jitter performance value of <1 ps.
Copyright © 2008, Texas Instruments Incorporated
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