CDCE62005 Datasheet, PDF (45/76 Pages) Texas Instruments – Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008
Output Dividers
Figure 29 shows that each output channel provides a 7-bit divider and digital phase adjust block. Table 23 lists
the divide ratios supported by the output divider for each output channel. Figure 30 illustrates the output divider
architecture in detail. The Prescaler provides an array of low noise dividers with duty cycle correction. The
Integer Divider includes a final divide by two stage which is used to correct the duty cycle of the /1–/8 stage. The
output divider’s maximum input frequency is limited to 1.175GHz. If the divider is bypassed (divide ratio = 1) then
the maximum frequency of the output channel is 1.5GHz.
Registers 0 - 4
12 11 10 9 8 7 6
Registers 0 - 4
20
Sync
Pulse
(internally generated )
From
Output
MUX
Enable
Digital Phase Adjust (7-bits)
Output Divider (7-bits)
To
Output
Buffer
Registers 0 - 4
19 18 17 16 15 14 13
Figure 29. CDCE62005 Output Divider and Phase Adjust
Registers 0 - 4
14 13
Registers 0 - 4
17 16 15
Registers 0 - 4
19 18
From
Output
MUX
/2-/5
Prescaler
/1 - /8
/2
00
Integer Divider
10
01
To
Output
Buffer
Figure 30. CDCE62005 Output Divider Architecture
Copyright © 2008, Texas Instruments Incorporated
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