K4N56163QF Datasheet, PDF (67/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
Command Truth Table.
Command truth table.
Function
CKE
Previous Current ^CS
Cycle Cycle
RAS
CAS
WE
BA0
BA1
A11
A10 A9 - A0 Notes
(Extended) Mode Register Set
H
H
L
L
L
L BA
OP Code
1,2
Refresh (REF)
H
H
L
L
L
HX
X
X
X
1
Self Refresh Entry
H
L
L
L
L
HX
X
X
X
1
Self Refresh Exit
H
X
X
X
L
H
X
X
X
X
1,7
L
H
H
H
Single Bank Precharge
H
H
L
L
H
L BA
X
L
X
1,2
Precharge all Banks
H
H
L
L
H
L
X
X
H
X
1
Bank Activate
H
H
L
L
H
H BA
Row Address
1,2
Write
H
H
L
H
L
L BA Column L Column 1,2,3,
Write with Auto Precharge
H
H
L
H
L
L BA Column H Column 1,2,3,
Read
H
H
L
H
L
H BA Column L Column 1,2,3
Read with Auto-Precharge
H
H
L
H
L
H BA Column H Column 1,2,3
No Operation
H
X
L
H
H
HX
X
X
X
1
Device Deselect
H
X
H
X
X
XX
X
X
X
1
Power Down Entry
H
X
X
X
H
L
X
X
X
X
1,4
L
H
H
H
Power Down Exit
H
X
X
X
L
H
X
X
X
X
1,4
L
H
H
H
1. All gDDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode
Register.
3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes inter-
rupted by a Write"
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements outlined
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. “X” means “H or L (but a defined logic level)”.
7. Self refresh exit is asynchronous.
8. VREF must be maintained during Self Refresh operation.
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Rev 1.6 (Apr. 2005)