K4N56163QF Datasheet, PDF (60/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates
the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering precharge power-
down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down
mode, CKE low and a stable clock signal must be maintained at the inputs of the gDDR2 SDRAM, and ODT should be in
a valid state but all other input signals are “Don’t Care”. CKE low must be maintained until tCKE has been satisfied.
Power-down duration is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command).
CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-
down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined at AC spec table of
this data sheet.
Basic Power Down Entry and Exit timing diagram
CK/CK
CKE
Command
t_IS t_IH
VIH(AVC_IH) _(DC)
VALID
t_IS t_IH
VIL(AC)
NOP
t_CKE
t_CKE
Enter Power-Down mode
t_IH
VIL(DC)
t_IS
VIH(AC)
NOP
VALID
t_XP, t_XARD,
t_XARDS
t_CKE
Exit Power-Down mode
t_IH
VIH(DC)
VALID
t_IS t_IH
VIH(AC)
VIH(DC)
VALID
Don’t Care
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Rev 1.6 (Apr. 2005)