K4N56163QF Datasheet, PDF (30/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
1
0
0
1 Increase by 1 step
Decrease by 1 step
1
0
1
0 Decrease by 1 step
Decrease by 1 step
Other Combinations
Reserved
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the following timing
diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by
MRS addressing mode (ie. sequential or interleave).
OCD adjust mode
CMD EMRS
NOP
CK
CK
WL
DQS_in
DQ_in
DM
NOP
NOP
NOP
DQS
tDS tDH
VIH(AC) _VIH(DC)
DT0 _DT1 DT2 DT3
VIL(AC) _VIL(DC)
OCD calibration mode exit
NOP
EMRS
NOP
WR
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure gDDR2 SDRAM Driver impedance. In this
mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers are turned-off tOIT after
“OCD calibration mode exit” command as the following timing diagram.
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Rev 1.6 (Apr. 2005)