K4N56163QF Datasheet, PDF (41/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
Seamless Burst Read Operation: RL = 5, AL = 2, and CL = 3, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
Post CAS
READ A0
NOP
Post CAS
READ A4
NOP
NOP
DQS
DQs
AL = 2
RL = 5
CL =3
NOP
NOP
NOP
NOP
DOUT A₀ DOUT A₁ DOUT A₂ DOUT A₃ DOUT A₄ DOUT A₅ DOUT A₆
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation,
and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the
banks are activated.
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Rev 1.6 (Apr. 2005)