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K4N56163QF Datasheet, PDF (35/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM
K4N56163QF-GC
256M gDDR2 SDRAM
Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock.
The bank addresses BA0 and BA1 are used to select the desired bank. The row address A0 through A12 is used to deter-
mine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write
operation can be executed. Immediately after the bank active command, the gDDR2 SDRAM can accept a read or write
command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specifica-
tion, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the
device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 are
supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied
to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time
interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the
device (tRC). The minimum time interval between Bank Activate commands is tRRD.
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CK / CK
..........
Internal RAS-CAS delay (>= tRCDmin)
ADDRESS
Bank A
Bank A
Bank B
Bank B . . . . . . . .B. a. nk A
Row Addr. Col. Addr. Row Addr. Col. Addr.
Addr.
RCD
=1
CAS-CAS delay time (tCCD)
additive latency delay (AL)
Read Begins
RAS - RAS delay time (>= tRRD)
Bank B
Addr.
Bank A
Row Addr.
COMMAND
Bank A
Activate
: “H” or “L”
Post CAS
Read A
Bank B
Activate
Post CAS
Read B
. . . . . . . .B.a.nk A
Precharge
Bank B
Precharge
Bank Active (>= tRAS)
Bank Precharge time (>= tRP)
RAS Cycle time (>= tRC)
Bank A
Active
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Rev 1.6 (Apr. 2005)