K4N56163QF Datasheet, PDF (45/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
Seamless Burst Write Operation: RL = 5, WL = 4, BL=4
256M gDDR2 SDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD ^{Post CAS}
WRITE A0
NOP
Post CAS
WRITE A1
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ’s
WL = RL - 1 = 4
DIN A₀ DIN A₁ DIN A₂ DIN A₃ DIN A₀ DIN A₁ DIN A₂ DIN A₃
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation,
every four clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks
are activated.
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Rev 1.6 (Apr. 2005)