K4N56163QF Datasheet, PDF (47/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on gDDR2 SDRAMs, Consistent with the imple-
mentation on gDDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-direc-
tional manner, is internally loaded identically to data bits to insure matched system timing. DM of x16 bit organization is
not used during read cycles.
Data Mask Timing
DQS/
DQS
DQ
DM
VIH(ac) V_IH(dc)
VIL(ac) VIL(dc)
tDS tDH
VIH(ac)_VIH(dc)
VIL(ac) ^VIL^(dc)
tDS tDH
Data Mask Function, WL=3, AL=0, BL = 4 shown
Case 1 : min tDQSS
CK
CK
COMMAND
Write
tDQSS
tWR
DQS/DQS
DQ
DM
Case 2 : max tDQSS
DQS/DQS
DQ
DM
tDQSS
- 47 -
Rev 1.6 (Apr. 2005)