K4N56163QF Datasheet, PDF (38/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory loca-
tions (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length.
gDDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is
supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either
sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS, which is similar to the DDR
SDRAM operation. Seamless burst read or write operations are supported. Unlike DDR devices, interruption of a burst
read or write cycle during BL = 4 mode operation is prohibited. However in case of BL = 8 mode, interruption of a burst
read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the
Burst Stop command is not supported on gDDR2 SDRAM devices.
Burst Length and Sequence
BL = 4
Burst Length
4
Starting Address (A1 A0)
00
01
10
11
Sequential Addressing (decimal) Interleave Addressing (decimal)
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
BL = 8
Burst Length
8
Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal)
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Note: Page length is a function of I/O organization and column addressin
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Rev 1.6 (Apr. 2005)