K4N56163QF Datasheet, PDF (44/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
Tn
CK/CK
CMD
CAS
WRITE A
NOP
DQS
DQs
WL = RL - 1 = 2
NOP
< = t_DQSS
NOP
NOP
NOP
Completion of
the Burst Write
Precharge
NOP
Bank A
Activate
DIN A₀ DIN A₁ DIN A₂ DIN A₃
> = WR
> = tRP
Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4
T0
CK/CK
CMD ^NOP
T1
T2
T3
T4
T5
Write to Read = CL - 1 + BL/2 + tWTR
NOP
NOP
NOP
Post CAS
READ A
NOP
T6
NOP
T7
NOP
T8
T9
NOP
DQS
WL = RL - 1 = 4
AL = 2
> = tWTR
RL =5
CL = 3
DQ
DOUT A₀ DOUT A₁ DOUT A₂ DOUT A₃
DIN
The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 + tWTR]. This
tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense
amplifiers in the array. tWTR is defined in AC spec table of this data sheet.
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Rev 1.6 (Apr. 2005)