K4N56163QF Datasheet, PDF (53/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Com-
mand or the auto-precharge function. When a Read or a Write Command is given to the gDDR2 SDRAM, the CAS timing
accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest
possible moment during the burst read or write cycle. If A10 is low when the READ or WRITE Command is issued, then
normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If
A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-pre-
charge, a Read Command will execute as normal with the exception that the active bank will begin to precharge on the ris-
ing edge which is CAS latency (CL) clock cycles before the end of the read burst.
Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto precharge
command will not begin until the last data of the burst write sequence is properly stored in the memory array.
This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon
CAS latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the
Precharge operation until the array restore operation has been completed (tRAS satisfied) so that the auto precharge com-
mand may be issued with any read or write command.
Burst Read with Auto Precharge
If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The gDDR2 SDRAM
starts an auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than the read with AP command if
tRAS(min) and tRTP are satisfied.
If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRAS(min) is satis-
fied.
If tRTP(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRTP(min) is satis-
fied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at
the next rising clock edge after this event). So for BL = 4 the minimum time from Read_AP to the next Activate command
becomes AL + (tRTP + tRP)* (see example 2) for BL = 8 the time from Read_AP to the next Activate is AL + 2 + (tRTP +
tRP)*, where “*” means: “rouded up to the next integer”. In any event internal precharge does not start earlier than two
clocks after the last 4-bit prefetch.
A new bank activate (command) may be issued to the same bank if the following two conditions are satisfied simulta-
neously.
(1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
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Rev 1.6 (Apr. 2005)