K4N56163QF Datasheet, PDF(23/73 Page) Samsung semiconductor

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K4N56163QF Datasheet, PDF (23/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

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K4N56163QF-GC

256M gDDR2 SDRAM

1. Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS.

2. The gDDR2 SDRAM is now ready for normal operation.

*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.

Initialization Sequence after Power Up

/CK

CKE

ODT

tCHtCL

tIS

VIH(ac)

Command

NOP

PRE

ALL

EMRS

MRS

PRE

ALL

REF

400ns

tRP

tMRD

tRP

DLL

ENABLE

DLL

RESET

REF

tRFC

min. 200 Cycle

MRS

EMRS

ANY

CMD

tMRD

Follow OCD

tOIT

Flowchart

OCD

Default

OCD

CAL. MODE

EXIT

Programming the Mode Register

For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR) are user

defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable func-

tion, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended strobe, and OCD(off chip driver

impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set

(EMRS) command. Contents of the Mode Register(MR) or Extended Mode Registers(EMR(#)) can be altered by re-exe-

cuting the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all

variables must be redefined when the MRS or EMRS commands are issued.

MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed

any time after power-up without affecting array contents.

- 23 -

Rev 1.6 (Apr. 2005)

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