K4N56163QF Datasheet, PDF (24/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
gDDR2 SDRAM Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of gDDR2 SDRAM. It controls CAS latency,
burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make gDDR2 SDRAM
useful for various applications. The default value of the mode register is not defined, therefore the mode register must be
written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0 and
BA1, while controlling the state of address pins A0 ~ A15. The gDDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to com-
plete the write operation to the mode register. The mode register contents can be changed using the same command and
clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is
divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst
lengths. The burst length decodes are compatible with gDDR SDRAM. Burst address sequence type is defined by A3,
CAS latency is defined by A4 ~ A6. The gDDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is
used for DLL reset. A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 ~ A11.
Refer to the table for specific codes.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
RFU 0 PD
tWR
DLL TM
CAS Latency
BT
Burst Length
Active Power
A12
Down exit time
0 Fast exit (use tXARD)
1 Slow exit (use tXARDS)
BA1
0
0
1
1
BA0
0
1
0
1
MRS Mode
MRS
EMRS (1)
EMRS (2) : Reserved
EMRS (3) : Reserved
Write Recovery for Auto Precharge
A11 A10 A9
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MRS Select
Reserved
Reserved
Reserved
4
5
6
7
8
Test Mode
A7
mode
0 Normal
1
Test
Burst Type
A3
Type
0 Sequential
1 Interleave
DLL
A8
0
1
DLL Reset
No
Yes
Burst Length
A2 A1 A0 Burst Length
010
4
011
8
CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
Latency
Reserved
Reserved
Reserved
Reserved
4
5
6
7
*1 : A13 is reserved for future use and must be programmed to 0 when setting the mode register.
BA2 and A14 are not used for 512Mb, but used for 1Gb and 2Gb gDDR2 SDRAMs. A15 is reserved for future
usage.
*2 : WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles is
calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next integer
(WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL.
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Rev 1.6 (Apr. 2005)