K4N56163QF Datasheet, PDF (11/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted, 0°C ≤ Tc ≤85°C )
Parameter
Symbol
Test Condition
Version
- 25 - 30 - 37
Operating Current
(One Bank Active)
ICC1
Burst Length=4 tRC ≥ tRC(min). IOL=0mA, tCC= tCC(min).
DQ,DM,DQS inputs changing twice per clock cycle.
Address and control inputs changing once per clock
150
135
120
cycle
Precharge Standby Current
in Power-down mode
Precharge Standby Current
in Non Power-down mode
Active Standby Current
power-down mode
ICC2P
CKE ≤ VIL(max), tCC= tCC(min)
10
CKE ≥ VIH(min), CS ≥ VIH(min),tCC= tCC(min)
ICC2N
Address and control inputs changing once per clock
45
45
40
cycle
ICC3P
CKE ≤ VIL(max), tCC= tCC(min)
50
50
50
Active Standby Current in
in Non Power-down mode
Operating Current
( Burst Mode)
Refresh Current
Self Refresh Current
Operating Current
(4Bank interleaving)
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min)
DQ,DM,DQS inputs changing twice per clock cycle.
Address and control inputs changing once per clock
cycle
85
85
80
ICC4
IOL=0mA ,tCC= tCC(min),
Page Burst, All Banks activated. DQ,DM,DQS inputs
300
280
260
changing twice per clock cycle. Address and control
inputs changing once per clock.
ICC5
tRC≥ tRFC
190
180
160
ICC6
CKE ≤ 0.2V
10
ICC7
Burst Length=4 tRC ≥ tRC(min). IOL=0mA, tCC= tCC(min).
DQ,DM,DQS inputs changing twice per clock cycle.
Address and control inputs changing once per clock
430
400
350
cycle
Note : 1. Measured with outputs open and ODT off
2. Refresh period is 32ms
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
- 11 -
Rev 1.6 (Apr. 2005)