K4N56163QF Datasheet, PDF (64/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
Asynchronous CKE Low Event
DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asynchronously
drops “LOW” during any valid operation DRAM is not guaranteed to preserve the contents of array. If this event occurs,
memory controller must satisfy DRAM timing specification tDelay before turning off the clocks. Stable clocks must exist at
the input of DRAM before CKE is raised “HIGH” again. DRAM must be fully re-initialized (steps 4 thru 13) as described in
initialization sequence. DRAM is ready for normal operation after the initialization sequence. See AC timing parametric
table for tDelay specification
CK#
CK
CKE
tCK
tDelay
Stable clocks
CKE asynchronously drops low
Clocks can be turned
off after this point
- 64 -
Rev 1.6 (Apr. 2005)