K4N56163QF Datasheet, PDF (59/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
Power-Down
Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE is not
allowed to go low while mode register or extended mode register command time, or read or write operation is in progress.
CKE is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, or auto-refresh
is in progress, but power-down IDD spec will not be applied until finishing those operations. Timing diagrams are shown in
the following pages with details for entry into power down.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down
mode for proper read operation. DRAM design guarantees it’s DLL in a locked state with any CKE intensive operations as
long as DRAM controller complies with DRAM specifications. Following figures show two examples of CKE intensive appli-
cations. In both examples, DRAM maintains DLL in a locked state throughout the period.
<Example of CKE instensive environment 1>
CK
CK
CKE
tCKE
tCKE
DRAM maintains DLL in locked state with intensive CKE operation
<Example of CKE Iintensive enviroment 2>
CK
CK
CKE
tXP
CMD
REF
REF
tCKE
REF
tREFI = 7.8 us
tREFI = 7.8 us
The pattern shown above can repeat over a long period of time. With this pattern,
DRAM maintains DLL in a locked state with temperature and voltage drift.
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Rev 1.6 (Apr. 2005)