K4N56163QF Datasheet, PDF (36/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and
CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether the access cycle is a read
operation (WE high) or a write operation (WE low).
The gDDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read
or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of
the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of 2048 bits (defined by CA0-CA9,
CA11). The page length of 2048 is divided into 512 or 256 uniquely addressable boundary segments depending on burst
length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4-bit or 8 bit burst operation will occur entirely within one of the
512 or 256 groups beginning with the column address supplied to the device during the Read or Write Command (CA0-
CA9, CA11). The second, third and fourth access will also occur within this group segment, however, the burst order is a
function of the starting address, and the burst sequence.
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL
= 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes
interrupted by a write with 4 bit burst boundry respectively. The minimum CAS to CAS delay is defined by tCCD, and is a
minimum of 2 clocks for read or write cycles.
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Rev 1.6 (Apr. 2005)