K4N56163QF Datasheet, PDF (16/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
3. gDDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in the following figure.
VDDQ
DUT
DQ
DQS, DQS ^Output
Test point
25Ω
V_TT = V_DDQ/2
<Slew Rate Test Load>
4. Differential data strobe
gDDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS
“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the gDDR2 SDRAM
pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling
edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data
strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm
resisor to insure proper operation.
DQS/
DQS
DQ
DM
DQS
t_DQSH
t_DQSL
DQS
t_WPRE
VIH(ac)
D
VIL(ac)
t_DS
DMin
D
VIH(ac) ^tDS
DMin
VIL(ac)
VIH(dc)
D
VIL(dc)
t_DH
DMin
<Data input (write) timing>
t_WPST
D
t_DH
VIH(dc)
DMin
VIL(dc)
CK
CK/CK
CK
DQS/DQS
DQ
t_CH
t_CL
DQS
DQS
t_RPRE
t_DQSQmax
Q
t_QH
Q
Q
t_DQSQmax
<Data output (read) timing>
t_RPST
Q
t_QH
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
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Rev 1.6 (Apr. 2005)