K4N56163QF Datasheet, PDF (37/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in gDDR2
SDRAM. In this operation, the gDDR2 SDRAM allows a CAS read or write command to be issued immediately after the
RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD, period). The command is held for the
time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of
AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater
than 0) must be written into the EMR(1). The Write Latency (WL) is always defined as RL - 1 (read latency -1) where read
latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL allow
seamless bursts (refer to seamless operation timing diagram examples in Read burst and Write burst section)
Examples of posted CAS operation
Example 1 Read followed by a write to the same bank
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]
-1 0 1 2 3 4 5 6 7 8 9 10 11 12
CK/CK
CMD
DQS/DQS
DQ
Active
A-Bank
Read
A-Bank
AL = 2
Write
A-Bank
CL = 3
WL = RL -1 = 4
> = tRCD
RL = AL + CL = 5
Dout0 Dout1 Dout2 Dout3
> = tRAC
Din0 Din1 Din2 Din3
Example 2 Read followed by a write to the same bank
[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]
-1 0 1 2 3 4 5 6 7 8 9 10 11 12
CK/CK
CMD
DQS/DQS
DQ
Active
A-Bank
AL = 0
Read
A-Bank
CL = 3
Write
A-Bank
WL = RL -1 = 2
> = tRCD
RL = AL + CL = 3
Dout0 Dout1 Dout2 Dout3
> = tRAC
Din0 Din1 Din2 Din3
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Rev 1.6 (Apr. 2005)