K4N56163QF Datasheet, PDF (13/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
256M gDDR2 SDRAM
Parameter
Symbol
DQ output access time from CK/CK tAC
DQS output access time from CK/CK tDQSCK
CK high-level width
tCH
CK low-level width
tCL
CK half period
tHP
Clock cycle time, CL=x
tCK
DQ and DM input hold time
tDH
DQ and DM input setup time
tDS
Control & Address input pulse width
for each input
tIPW
DQ and DM input pulse width for
each input
tDIPW
Data-out high-impedance time from
CK/CK
tHZ
DQS low-impedance time from CK/
CK
tLZ
(DQS)
DQ low-impedance time from CK/CK tLZ(DQ)
DQS-DQ skew for DQS and
associated DQ signals
tDQSQ
DQ hold skew factor
tQHS
DQ/DQS output hold time from DQS tQH
Write command to first DQS latching
transition
tDQSS
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS falling edge to CK setup time
tDSS
DQS falling edge hold time from CK
tDSH
Mode register set command cycle
time
tMRD
Write postamble
tWPST
Write preamble
tWPRE
- 25
min
max
-400
400
-350
+350
0.45
0.55
0.45
0.55
min
(tCL, tCH)
x
2.5
8.0
175
x
50
x
0.6
x
- 30
min
max
-450
+450
-400
+400
0.45
0.55
0.45
0.55
min
(tCL, tCH)
x
3.0
8.0
175
x
50
x
0.6
x
- 37
min
max
-500
+500
-450
+450
0.45
0.55
0.45
0.55
min
(tCL, tCH)
x
3.75
8.0
225
x
100
x
0.6
x
Units
ps
ps
tCK
tCK
ps
ns
ps
ps
tCK
Notes
20,21
24
15,16,17
15,16,17
0.35
x
0.35
x
0.35
x
tCK
x
tAC max
x
tAC max
x
tAC max
ps
tAC min
tAC max
tAC min
tAC max
tAC min tAC max
ps
27
2*tAC min tAC max
2*tAC min tAC max
2* tACmin tAC max
ps
27
x
280
x
310
x
340
ps
22
x
tHP -
tQHS
WL
-0.25
0.35
0.35
0.2
0.2
380
x
WL
+0.25
x
x
x
x
x
tHP -
tQHS
WL
-0.25
0.35
0.35
0.2
0.2
410
x
WL
+0.25
x
x
x
x
x
tHP -
tQHS
WL
-0.25
0.35
0.35
0.2
0.2
440
x
WL
+0.25
x
x
x
x
ps
21
ps
tCK
tCK
tCK
tCK
tCK
2
x
2
x
2
x
tCK
0.4
0.6
0.35
x
0.4
0.6
0.35
x
0.4
0.6
0.35
x
tCK
19
tCK
- 13 -
Rev 1.6 (Apr. 2005)