K4N56163QF Datasheet, PDF(43/73 Page) Samsung semiconductor

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K4N56163QF Datasheet, PDF (43/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

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K4N56163QF-GC

256M gDDR2 SDRAM

Burst Write Operation

The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the

clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL)

minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the

WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the

preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on succes-

sive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any addi-

tional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete.

The time from the completion of the burst write to bank precharge is the write recovery time (WR).

gDDR2 SDRAM pin timings are specified for either single ended mode or differen-tial mode depending on the setting of

the EMRS âEnable DQSâ mode bit; timing advantages of differential mode are realized in system design. The method by

which the gDDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are

measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are

measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by

design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary

pin, DQS, must be tied externally to VSS through a 20 ohm to 10K ohm resistor to insure proper operation.

DQS/

DQS

tWPRE

tDQSH

tDQSL

VIH(ac)

VIL(ac)

tDS

DMin

tDS

VIH(ac)

DMin

VIL(ac)

VIH(dc)

VIL(dc)

tDH

DMin

tWPST

tDH

VIH(dc)

DMin

VIL(dc)

Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4

CK/CK

CMD

Posted CAS

WRITE A

NOP

DQS

DQs

WL = RL - 1 = 4

NOP

< = tDQSS

NOP

Completion of

the Burst Write

Precharge

DIN A0 DIN A1 DIN A2 DIN A3

> = WR

- 43 -

Rev 1.6 (Apr. 2005)

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