K4N56163QF Datasheet, PDF (17/73 Pages) Samsung semiconductor – 256Mbit gDDR2 SDRAM

K4N56163QF-GC
256M gDDR2 SDRAM
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels,
but the related specifications and device operation are guaranteed for the full voltage range specified.
Specific Notes for dedicated AC parameters
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power
down exit timing. tXARDS is expected to be used for slow active power down exit timing.
10. AL = Additive Latency
11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been
satisfied.
12. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
13. Timings are guaranteed with command/address input slew rate of 1.0 V/ns.
14. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
15. Timings are guaranteed with data, mask, and (DQS in singled ended mode) input slew rate of 1.0 V/ns.
16. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential
slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode.
17. tDS and tDH (data setup and hold) derating
1) Input waveform timing is referenced from the input signal crossing at the V_IH(AC) level for a rising signal and V_IL(AC) for a
falling signal applied to the device under test.
2) Input waveform timing is referenced from the input signal crossing at the V_IH(DC) level for a rising signal and V_IL(DC) for a
falling signal applied to the device under test.
DQS
DQS
tDS tDH
tDS tDH
<Data setup/hold timing>
V_DDQ
V_IH(AC) min
V_IH(DC) min
V_REF
V_IL(DC) max
V_IL(AC) max
V_SS
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Rev 1.6 (Apr. 2005)