HD64F3664BPV Datasheet, PDF (82/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
Table 3.1 Exception Sources and Vector Address
Relative Module
RES pin
Watchdog timer

External interrupt
pin
CPU
Address break
CPU
External interrupt
pin
Timer A

Timer W
Timer V
SCI3
IIC
A/D converter
Exception Sources
Reset
Vector
Number Vector Address
0
H'0000 to H'0001
Priority
High
Reserved for system use
NMI
1 to 6
7
Trap instruction (#0)
8
(#1)
9
(#2)
10
(#3)
11
Break conditions satisfied
12
Direct transition by executing the 13
SLEEP instruction
IRQ0
14
IRQ1
15
IRQ2
16
IRQ3
17
WKP
18
Overflow
19
Reserved for system use
20
Input capture A/compare match A 21
Input capture B/compare match B
Input capture C/compare match C
Input capture D/compare match D
Timer W overflow
Timer V compare match A
22
Timer V compare match B
Timer V overflow
SCI3 receive data full
23
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
Data transfer end
24
Address inequality
Stop conditions detected
A/D conversion end
25
H'0002 to H'000D
H'000E to H'000F
H'0010 to H'0011
H'0012 to H'0013
H'0014 to H'0015
H'0016 to H'0017
H'0018 to H'0019
H'001A to H'001B
H'001C to H'001D
H'001E to H'001F
H'0020 to H'0021
H'0022 to H'0023
H'0024 to H'0025
H'0026 to H'0027
H'0028 to H'0029
H'002A to H'002B
H'002C to H'002D
H'002E to H'002F
H'0030 to H'0031
H'0032 to H'0033 Low
Rev. 6.00 Mar. 24, 2006 Page 52 of 412
REJ09B0142-0600