HD64F3664BPV Datasheet, PDF (66/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 2 CPU
(1) Register Direct—Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
(2) Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.
(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
(a) Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits of
which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added
to the address register contents (32 bits) and the sum is stored in the address register. The value
added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword
access, the register value should be even.
(b) Register indirect with pre-decrement—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in
the instruction code, and the lower 24 bits of the result is the address of a memory operand. The
result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word
access, or 4 for longword access. For the word or longword access, the register value should be
even.
Rev. 6.00 Mar. 24, 2006 Page 36 of 412
REJ09B0142-0600