HD64F3664BPV Datasheet, PDF (148/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 9 I/O Ports
9.1.3 Port Data Register 1 (PDR1)
PDR1 is a general I/O port data register of port 1.
Initial
Bit
Bit Name Value R/W Description
7
P17
0
R/W PDR1 stores output data for port 1 pins.
6
P16
0
5
P15
0
4
P14
0
3

1
2
P12
0
R/W If PDR1 is read while PCR1 bits are set to 1, the value
R/W ^{stored in PDR1 are read. If PDR1 is read while PCR1}
bits are cleared to 0, the pin states are read regardless
R/W _{of the value stored in PDR1.}

Bit 3 is a reserved bit. This bit is always read as 1.
R/W
1
P11
0
R/W
0
P10
0
R/W
9.1.4 Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports.
Initial
Bit
Bit Name Value R/W Description
7
PUCR17 0
6
PUCR16 0
5
PUCR15 0
4
PUCR14 0
3

1
R/W Only bits for which PCR1 is cleared are valid. The pull-
R/W ^{up MOS of P17 to P14 and P12 to P10 pins enter the}
on-state when these bits are set to 1, while they enter
R/W _{the off-state when these bits are cleared to 0.}
R/W _{Bit 3 is a reserved bit. This bit is always read as 1.}

2
PUCR12 0
R/W
1
PUCR11 0
R/W
0
PUCR10 0
R/W
Rev. 6.00 Mar. 24, 2006 Page 118 of 412
REJ09B0142-0600