HD64F3664BPV Datasheet, PDF (17/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14.8.4 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode ..................................................................................... 231
Section 15 I²C Bus Interface (IIC) .....................................................................233
15.1 Features............................................................................................................................. 233
15.2 Input/Output Pins.............................................................................................................. 235
15.3 Register Descriptions........................................................................................................ 236
15.3.1 I²C Bus Data Register (ICDR) .......................................................................... 236
15.3.2 Slave Address Register (SAR).......................................................................... 238
15.3.3 Second Slave Address Register (SARX) .......................................................... 238
15.3.4 I²C Bus Mode Register (ICMR)........................................................................ 239
15.3.5 I²C Bus Control Register (ICCR)...................................................................... 242
15.3.6 I²C Bus Status Register (ICSR)......................................................................... 245
15.3.7 Timer Serial Control Register (TSCR) ............................................................. 248
15.4 Operation .......................................................................................................................... 249
15.4.1 I²C Bus Data Format ......................................................................................... 249
15.4.2 Master Transmit Operation ............................................................................... 251
15.4.3 Master Receive Operation................................................................................. 253
15.4.4 Slave Receive Operation................................................................................... 255
15.4.5 Slave Transmit Operation ................................................................................. 258
15.4.6 Clock Synchronous Serial Format .................................................................... 259
15.4.7 IRIC Setting Timing and SCL Control ............................................................. 260
15.4.8 Noise Canceler.................................................................................................. 261
15.4.9 Sample Flowcharts............................................................................................ 262
15.5 Usage Notes ...................................................................................................................... 266
Section 16 A/D Converter..................................................................................275
16.1 Features............................................................................................................................. 275
16.2 Input/Output Pins.............................................................................................................. 277
16.3 Register Description ......................................................................................................... 278
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .......................................... 278
16.3.2 A/D Control/Status Register (ADCSR) ............................................................ 279
16.3.3 A/D Control Register (ADCR) ......................................................................... 280
16.4 Operation .......................................................................................................................... 281
16.4.1 Single Mode...................................................................................................... 281
16.4.2 Scan Mode ........................................................................................................ 281
16.4.3 Input Sampling and A/D Conversion Time ...................................................... 282
16.4.4 External Trigger Input Timing.......................................................................... 283
16.5 A/D Conversion Accuracy Definitions ............................................................................. 284
16.6 Usage Notes ...................................................................................................................... 286
Rev. 6.00 Mar. 24, 2006 Page xv of xxviii