HD64F3664BPV Datasheet, PDF (280/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 I²C Bus Interface (IIC)
(a) I²C bus format (FS = 0 or FSX = 0)
S
SLA
R/W A
DATA
1
7
11
n
1
A
1
m
A/A P
11
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
(b) I²C bus format (start condition retransmission, FS = 0 or FSX = 0)
S
SLA
R/W A
DATA
1
7
11
n1
A/A S
11
SLA
R/W A
DATA
7
11
n2
A/A P
11
1
m1
1
m2
n1 and n2: transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: transfer frame count (m1 and m2 ≥ 1)
Figure 15.3 I²C Bus Data Formats (I²C Bus Formats)
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
SLA R/W A
DATA
A
DATA
A/A
P
Figure 15.4 I²C Bus Timing
[Legend]
S: Start condition. The master device drives SDA from high to low while SCL is high
SLA: Slave address
R/W: Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0
A: Acknowledge. The receiving device drives SDA
DATA: Transferred data
P: Stop condition. The master device drives SDA from low to high while SCL is high
Rev. 6.00 Mar. 24, 2006 Page 250 of 412
REJ09B0142-0600