HD64F3664BPV Datasheet, PDF (252/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3)
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.13 shows a sample flowchart
for serial data reception.
Start reception
[1] Read the OER flag in SSR to determine
if there is an error. If an overrun error
Read OER flag in SSR
[1]
has occurred, execute overrun error
processing.
OER = 1
No
Yes
[4]
Error processing
[2] Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR. When data is read from
RDR, the RDRF flag is automatically
(Continued below)
cleared to 0.
[3] To continue serial reception, before the
Read RDRF flag in SSR
[2]
MSB (bit 7) of the current frame is
received, reading the RDRF flag and
reading RDR should be finished. When
No
RDRF = 1
data is read from RDR, the RDRF flag
is automatically cleared to 0.
Yes
[4] If an overrun error occurs, read the
OER flag in SSR, and after performing
Read receive data in RDR
the appropriate error processing, clear
the OER flag to 0. Reception cannot be
Yes
All data received?
[3]
No
Clear RE bit in SCR3 to 0
<End>
[4]
Error processing
Overrun error processing
Clear OER flag in SSR to 0
<End>
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
Rev. 6.00 Mar. 24, 2006 Page 222 of 412
REJ09B0142-0600