HD64F3664BPV Datasheet, PDF (211/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 Timer W
12.5 Operation Timing
12.5.1 TCNT Count Timing
Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure
12.15 shows the timing when the external clock source is selected. The pulse width of the external
clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted
correctly.
φ
Internal
clock
Rising edge
TCNT input
clock
TCNT
N
N+1
N+2
Figure 12.14 Count Timing for Internal Clock Source
φ
External
clock
TCNT input
clock
TCNT
Rising edge
N
Rising edge
N+1
N+2
Figure 12.15 Count Timing for External Clock Source
Rev. 6.00 Mar. 24, 2006 Page 181 of 412
REJ09B0142-0600