HD64F3664BPV Datasheet, PDF (377/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Appendix A Instruction Set
Appendix
A.1 Instruction List
Operand Notation
Symbol
Rd
Rs
Rn
ERd
ERs
ERn
(EAd)
(EAs)
PC
SP
CCR
N
Z
V
C
disp
→
+
–
×
÷
∧
∨
Description
General (destination*) register
General (source*) register
General register*
General destination register (address register or 32-bit register)
General source register (address register or 32-bit register)
General register (32-bit register)
Destination operand
Source operand
Program counter
Stack pointer
Condition-code register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Displacement
Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
Addition of the operands on both sides
Subtraction of the operand on the right from the operand on the left
Multiplication of the operands on both sides
Division of the operand on the left by the operand on the right
Logical AND of the operands on both sides
Logical OR of the operands on both sides
Rev. 6.00 Mar. 24, 2006 Page 347 of 412
REJ09B0142-0600