HD64F3664BPV Datasheet, PDF (272/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 I²C Bus Interface (IIC)
15.3.5 I²C Bus Control Register (ICCR)
I²C bus control register (ICCR) consists of the control bits and interrupt request flags of I²C bus
interface.
Initial
Bit
Bit Name Value R/W Description
7
ICE
0
R/W I²C Bus Interface Enable
When this bit is set to 1, the I²C bus interface module is
enabled to send/receive data and drive the bus since it
is connected to the SCL and SDA pins. ICMR and
ICDR can be accessed.
When this bit is cleared, the module is halted and
separated from the SCL and SDA pins. SAR and SARX
can be accessed.
6
IEIC
0
R/W I²C Bus Interface Interrupt Enable
When this bit is 1, Interrupts are enabled by IRIC.
5
MST
0
R/W Master/Slave Select
4
TRS
0
R/W Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode of the I²C bus
format. In slave receive mode, the R/W bit in the first
frame immediately after the start automatically sets
these bits in receive mode or transmit mode by using
hardware. The settings can be made again for the bits
that were set/cleared by hardware, by reading these
bits. When the TRS bit is intended to change during a
transfer, the bit will not be switched until the frame
transfer is completed, including acknowledgement.
Rev. 6.00 Mar. 24, 2006 Page 242 of 412
REJ09B0142-0600