HD64F3664BPV Datasheet, PDF (101/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 4 Address Break
4.2 Operation
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an
interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the
address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt
request is accepted, interrupt exception handling starts after the instruction being executed ends.
The address break interrupt is not masked because of the I bit in CCR of the CPU.
Figures 4.2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Register setting
• ABRKCR = H'80
• BAR = H'025A
Program
0258 NOP
* 025A NOP
025C MOV.W @H'025A,R0
0260 NOP
0262 NOP
:
:
Underline indicates the address
to be stacked.
φ
Address
bus
Interrupt
request
NOP NOP MOV MOV
instruc- instruc- instruc- instruc-
tion
tion tion 1 tion 2 Internal
prefetch prefetch prefetch prefetch processing
Stack save
0258 025A 025C
025E
SP-2 SP-4
Interrupt acceptance
Figure 4.2 Address Break Interrupt Operation Example (1)
Rev. 6.00 Mar. 24, 2006 Page 71 of 412
REJ09B0142-0600