HD64F3664BPV Datasheet, PDF (323/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 17 EEPROM
17.4.7 Write Operations
There are two types write operations; byte write operation and page write operation. To initiate
the write operation, input 0 to R/W code following the slave address.
1. Byte Write
A write operation requires an 8-bit data of a 7-bit slave address with R/W code = "0". Then
the EEPROM sends acknowledgement "0" at the ninth bit. This enters the write mode. Then,
two bytes of the memory address are received from the MSB side in the order of upper and
lower. Upon receipt of one-byte memory address, the EEPROM sends acknowledgement "0"
and receives a following a one-byte write data. After receipt of write data, the EEPROM sends
acknowledgement "0". If the EEPROM receives a stop condition, the EEPROM enters an
internally controlled write cycle and terminates receipt of SCL and SDA inputs until
completion of the write cycle. The EEPROM returns to a standby mode after completion of
the write cycle.
The byte write operation is shown in figure 17.3.
SCL
1 2 34 5 6 7891
8 91
891
89
SDA
A15
A8
A7
A0
D7
D0
Start
condition
Slave address
R/W ACK
Upper memory
address
ACK
lower memory
address
ACK
Write Data
ACK
Stop
conditon
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
Figure 17.3 Byte Write Operation
2. Page Write
This LSI is capable of the page write operation which allows any number of bytes up to 8
bytes to be written in a single write cycle. The write data is input in the same sequence as the
byte write in the order of a start condition, slave address + R/W code, memory address (n), and
write data (Dn) with every ninth bit acknowledgement "0" output. The EEPROM enters the
page write operation if the EEPROM receives more write data (Dn+1) is input instead of
receiving a stop condition after receiving the write data (Dn). LSB 3 bits (A2 to A0) in the
EEPROM address are automatically incremented to be the (n+1) address upon receiving write
data (Dn+1). Thus the write data can be received sequentially.
Rev. 6.00 Mar. 24, 2006 Page 293 of 412
REJ09B0142-0600