HD64F3664BPV Datasheet, PDF (282/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 I²C Bus Interface (IIC)
9. Write the transmit data to ICDR. As indicating the end of the transfer, and so the IRIC flag is
cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in the step
[6]. Transmission of the next frame is performed in synchronization with the internal clock.
10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit
is 0). When there is data to be transmitted, go to the step [9] to continue next transmission.
When the slave device has not acknowledged (ACKB bit is set to 1), operate the step [12] to
end transmission.
12. Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from low
to high when SCL is high, and generates the stop condition.
Start condition generation
SCL
(master output)
SDA
(master output)
SDA
(slave output)
[5]
IRIC
1
2
3
4
5
6
7
8
9
Slave address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W ^[7]
A
1
2
Bit 7 Bit 6
Data 1
IRTR
ICDR
Address + R/W
Data 1
*
ICDR writing
prohibited
Normal
operation
User processing [4] Write BBSY = 1 [6] ICDR write
and SCP = 0
(start condition
issuance)
Note: * Data write timing in ICDR
[6] IRIC clearance
[9] IRIC clearance
[9] ICDR write
Figure 15.5 Master Transmit Mode Operation Timing Example
(MLS = WAIT = 0)
Rev. 6.00 Mar. 24, 2006 Page 252 of 412
REJ09B0142-0600