HD64F3664BPV Datasheet, PDF (303/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 I²C Bus Interface (IIC)
Stop condition Start condition
Along with ICDRT → ICDRR transfer
Cancel condition of SCL =
Low fixation is set.
SDA
A
Address
A
Data
SCL
89
123 4 5678 91 23 4
TRS bit
(b) TRS = 1
TDRE bit
TRS = 0 setting ICDR write
(a) TDRE = 0
Automatic TRS = 1 setting by
receiving R/W = 1
Figure 15.20 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode
 Restriction
Please carry out the following countermeasures when transmitting/receiving via the IIC bus
interface module.
(1) Please read the ICDR registers in receive mode, and write them in transmit mode.
(2) In receiving operation with master mode, please issue the start condition after clearing
the internal flag of the IIC bus interface module, using CLR3 to CLR0 bit of the
DDCSWR register on bus-free state (BBSY = 0).
Rev. 6.00 Mar. 24, 2006 Page 273 of 412
REJ09B0142-0600