HD64F3664BPV Datasheet, PDF (218/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 Timer W
Previous clock
New clock
Count clock
TCNT
N
N+1
N+2
N+3
The change in signal level at clock switching is
assumed to be a rising edge, and TCNT
increments the count.
Figure 12.25 Internal Clock Switching and TCNT Operation
5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the
first compare match occurs. Once a compare match occurs and this compare match changes the
values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the
values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and
the generation of the compare match A to D occur at the same timing, the writing to TCRW
has the priority. Thus, output change due to the compare match is not reflected to the FTIOA
to FTIOD pins. Therefore, when bit manipulation instruction is used to write to TCRW, the
values of the FTIOA to FTIOD pin output may result in an unexpected result. When TCRW is
to be written to while compare match is operating, stop the counter once before accessing to
TCRW, read the port 8 state to reflect the values of FTIOA to FTIOD output, to TOA to TOD,
and then restart the counter. Figure 12.26 shows an example when the compare match and the
bit manipulation instruction to TCRW occur at the same timing.
Rev. 6.00 Mar. 24, 2006 Page 188 of 412
REJ09B0142-0600