HD64F3664BPV Datasheet, PDF (327/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

SCL
SDA
1 2 34 5 6 7891
89
D7
D0
Section 17 EEPROM
1
89
D7
D0
Start
condition
Slave address
R/W ACK Read Data ACK · · · ·
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
Read Data ACK
Stop
conditon
Figure 17.7 Sequential Read Operation (when current address read is used)
17.5 Usage Notes
17.5.1 Data Protection at V_CC On/Off
When V_CC is turned on or off, the data might be destroyed by malfunction. Be careful of the
notices described below to prevent the data to be destroyed.
1. SCL and SDA should be fixed to V_CC or V_SS during V_CC on/off.
2. V_CC should be turned off after the EEPROM is placed in a standby state.
3. When V_CC is turned on from the intermediate level, malfunction is caused, so V_CC should be
turned on from the ground level (V_SS).
4. V_CC turn on speed should be longer than 10 us.
17.5.2 Write/Erase Endurance
The endurance is 10⁵ cycles/page (1% cumulative failure rate) in case of page programming and
10⁴ cycles/byte in case of byte programming. The data retention time is more than 10 years when a
device is page-programmed less than 10⁴ cycles.
Rev. 6.00 Mar. 24, 2006 Page 297 of 412
REJ09B0142-0600