HD64F3664BPV Datasheet, PDF (104/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 4 Address Break
When another interrupt request is accepted before an instruction to which an address break is set is
executed, exception handling of an address break interrupt is not executed. However, the ABIF bit
is set to 1 (see figure 4.4). Therefore the ABIF bit must be read during exception handling of an
address break interrupt.
[Register setting]
ABRKCR = H'80
BAR = H'0144
External interrupt
[Program]
001C 0900
:
:
0142 MOV.B #H'23,R1H
* 0144 MOV.B #H'45,R1H
0146 MOV.B #H'67,R1H
Underlined indicates the address to be stacked.
φ
Address bus
MOV MOV MOV
instruction instruction instruction Internal
prefetch prefetch prefetch processing
Stack save
Vector ^{Internal External interrupt}
fetch ^{processing acceptance}
0142 0144
0146
SP-2 SP-4
001C
0900
Address break
interrupt request
ABIF
External interrupt acceptance
Figure 4.4 Operation when Another Interrupt is Accepted at Address Break Setting
Instruction
Rev. 6.00 Mar. 24, 2006 Page 74 of 412
REJ09B0142-0600