HD64F3664BPV Datasheet, PDF (279/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 I²C Bus Interface (IIC)
Table 15.4 Flags and Transfer States
MST TRS BBSY ESTP STOP IRTR AASX AL
1/0 1/0 0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
1/0 1
0
0
0
0
0
1
1/0 1
0
0
1
0
0
0
0
1
0
0
0
1/0 1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1/0 1
0
0
0
0
0
0
1/0 1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1/0 0
1/0 1/0 0
0
0
AAS ADZ ACKB State
0
0
0
Idle state (flag clearing required)
0
0
0
Start condition issuance
0
0
0
Start condition established
0
0
0/1 Master mode wait
0
0
0/1 Master mode transmit/receive end
1/0 1/0 0
Arbitration lost
1
0
0
SAR match by first frame in slave
mode
1
1
0
General call address match
0
0
0
SARX match
0
0
0/1 Slave mode transmit/receive end
(except after SARX match)
0
0
0
Slave mode transmit/receive end
0
0
1
(after SARX match)
0
0
0/1 Stop condition detected
15.4 Operation
The I²C bus interface has serial and I²C bus formats.
15.4.1 I²C Bus Data Format
The I²C bus formats are addressing formats and an acknowledge bit is inserted. These are shown
in figures 15.3. Figure 15.5 shows the I²C bus timing. The first frame following a start condition
always consists of 8 bits.
Rev. 6.00 Mar. 24, 2006 Page 249 of 412
REJ09B0142-0600