HD64F3664BPV Datasheet, PDF (27/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Tables
Section 1 Overview
Table 1.1 Pin Functions ............................................................................................................ 9
Section 2 CPU
Table 2.1 Operation Notation ................................................................................................. 24
Table 2.2 Data Transfer Instructions....................................................................................... 25
Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 26
Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 27
Table 2.4 Logic Operations Instructions................................................................................. 28
Table 2.5 Shift Instructions..................................................................................................... 28
Table 2.6 Bit Manipulation Instructions (1)............................................................................ 29
Table 2.6 Bit Manipulation Instructions (2)............................................................................ 30
Table 2.7 Branch Instructions ................................................................................................. 31
Table 2.8 System Control Instructions.................................................................................... 32
Table 2.9 Block Data Transfer Instructions ............................................................................ 33
Table 2.10 Addressing Modes .................................................................................................. 35
Table 2.11 Absolute Address Access Ranges ........................................................................... 37
Table 2.12 Effective Address Calculation (1)........................................................................... 39
Table 2.12 Effective Address Calculation (2)........................................................................... 40
Section 3 Exception Handling
Table 3.1 Exception Sources and Vector Address .................................................................. 52
Table 3.2 Interrupt Wait States ............................................................................................... 62
Section 4 Address Break
Table 4.1 Access and Data Bus Used ..................................................................................... 69
Section 5 Clock Pulse Generators
Table 5.1 Crystal Resonator Parameters ................................................................................. 79
Section 6 Power-Down Modes
Table 6.1 Operating Frequency and Waiting Time................................................................. 85
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 89
Table 6.3 Internal State in Each Operating Mode................................................................... 90
Section 7 ROM
Table 7.1 Setting Programming Modes ................................................................................ 100
Table 7.2 Boot Mode Operation ........................................................................................... 102
Table 7.3 System Clock Frequencies for which Automatic Adjustment of
LSI Bit Rate is Possible ........................................................................................ 103
Rev. 6.00 Mar. 24, 2006 Page xxv of xxviii