HD64F3664BPV Datasheet, PDF (301/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 I²C Bus Interface (IIC)
• Notes on WAIT Function
 Conditions to cause this phenomenon
When both of the following conditions are satisfied, the clock pulse of the 9th clock could
be outputted continuously in master mode using the WAIT function due to the failure of
the WAIT insertion after the 8th clock fall.
(1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode
(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock
and the fall of the 8th clock.
 Error phenomenon
Normally, WAIT state will be cancelled by clearing the IRIC flag bit from 1 to 0 after the
fall of the 8th clock in WAIT state. In this case, if the IRIC flag bit is cleared between the
7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally.
Therefore, the WAIT state will be cancelled right after WAIT insertion on 8th clock fall.
 Restrictions
Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2
through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th
clock.
If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC
counter is turned to 1 or 0, please confirm the SCL pins are in the low state after the
counter value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure
15.18.)
SDA
SCL
A
Transmit/receive data
A
Transmit/receive
data
SCL =
9 1 2 3 4 5 6 7 8 _{'L' confirm} 9 1 2 3
BC2 to BC0
IRIC
(operation
example)
0 765 4321
IRIC flag clear available
0
765
IRIC clear
When BC2 to BC0 ≥ 2
clear IRIC
IRIC flag clear available
IRIC flag clear unavailable
Figure 15.18 IRIC Flag Clear Timing on WAIT Operation
Rev. 6.00 Mar. 24, 2006 Page 271 of 412
REJ09B0142-0600