HD64F3664BPV Datasheet, PDF (267/446 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 I²C Bus Interface (IIC)
The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF flags affects the status of the interrupt flags.
Initial
Bit
Bit Name Value R/W Description

TDRE

 Transmit Data Register Empty
[Setting conditions]
• In transmit mode, when a start condition is detected
in the bus line state after a start condition is issued
in master mode with the I²C bus format or serial
format selected
• When transmit mode (TRS = 1) is set without a
format
• When data is transferred from ICDRT to ICDRS
• When a switch is made from receive mode to
transmit mode after detection of a start condition
[Clearing conditions]
• When transmit data is written in ICDR in transmit
mode
• When a stop condition is detected in the bus line
state after a stop condition is issued with the I2C
bus format or serial format selected
• When a stop condition is detected with the I2C bus
format selected
• In receive mode

RDRF

 Receive Data Register Full
[Setting condition]
When data is transferred from ICDRS to ICDRR
[Clearing condition]
When ICDR (ICDRR) receive data is read in receive
mode
Rev. 6.00 Mar. 24, 2006 Page 237 of 412
REJ09B0142-0600